The patent documents 1, 2 disclose SiC semiconductor devices each including a junction field effect transistor (JFET) having a trench structure. FIG. 5A is a diagram showing a planar pattern of a conventional SiC semiconductor device. FIG. 5B is a cross-sectional view of the conventional SiC semiconductor device taken along line VB-VB in FIG. 5A. FIG. 5C is a cross-sectional view of the conventional SiC semiconductor device taken along line VC-VC in FIG. 5A.
As shown in FIG. 5A through FIG. 5C, after an n− type drift layer J2, a p+ type first gate region J3 and an n+ type source region J4 are formed in sequence on an n+ type SiC substrate J1, a trench J5 penetrating them is formed, and an n− type channel layer J6 and a p+ type second gate region J7 are formed in the trench J5. Although they are not shown, when a gate voltage applied to a gate electrode, which is electrically connected to the second gate region J7, is controlled, drain current flows between a source electrode which is electrically connected to the n+ type source region J4 and a drain electrode which is electrically connected to the n+ type SiC substrate J1.